The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC design and material have produced generations of ICs where each generation has smaller and more complex circuits than previous generations. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process has decreased. When a semiconductor device is scaled down through various technology nodes, challenges rise, such as reducing irregularities/distortions in features/patterns formed over a wafer and providing flexibility of forming features/patterns with various densities from an area to another area over a wafer.